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< //////////////////////////////////////////////////////////////////////
< ////                                                              ////
< ////  uart_debug_if.v                                             ////
< ////                                                              ////
< ////                                                              ////
< ////  This file is part of the "UART 16550 compatible" project    ////
< ////  http://www.opencores.org/cores/uart16550/                   ////
< ////                                                              ////
< ////  Documentation related to this project:                      ////
< ////  - http://www.opencores.org/cores/uart16550/                 ////
< ////                                                              ////
< ////  Projects compatibility:                                     ////
< ////  - WISHBONE                                                  ////
< ////  RS232 Protocol                                              ////
< ////  16550D uart (mostly supported)                              ////
< ////                                                              ////
< ////  Overview (main Features):                                   ////
< ////  UART core debug interface.                                  ////
< ////                                                              ////
< ////  Author(s):                                                  ////
< ////      - gorban@opencores.org                                  ////
< ////      - Jacob Gorban                                          ////
< ////                                                              ////
< ////  Created:        2001/12/02                                  ////
< ////                  (See log for the revision history)          ////
< ////                                                              ////
< //////////////////////////////////////////////////////////////////////
< ////                                                              ////
< //// Copyright (C) 2000, 2001 Authors                             ////
< ////                                                              ////
< //// This source file may be used and distributed without         ////
< //// restriction provided that this copyright statement is not    ////
< //// removed from the file and that any derivative work contains  ////
< //// the original copyright notice and the associated disclaimer. ////
< ////                                                              ////
< //// This source file is free software; you can redistribute it   ////
< //// and/or modify it under the terms of the GNU Lesser General   ////
< //// Public License as published by the Free Software Foundation; ////
< //// either version 2.1 of the License, or (at your option) any   ////
< //// later version.                                               ////
< ////                                                              ////
< //// This source is distributed in the hope that it will be       ////
< //// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
< //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
< //// PURPOSE.  See the GNU Lesser General Public License for more ////
< //// details.                                                     ////
< ////                                                              ////
< //// You should have received a copy of the GNU Lesser General    ////
< //// Public License along with this source; if not, download it   ////
< //// from http://www.opencores.org/lgpl.shtml                     ////
< ////                                                              ////
< //////////////////////////////////////////////////////////////////////
< //
< // CVS Revision History
< //
< // $Log: not supported by cvs2svn $
< // Revision 1.2  2001/12/12 22:17:30  gorban
< // some synthesis bugs fixed
< //
< // Revision 1.1  2001/12/04 21:14:16  gorban
< // committed the debug interface file
< //
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< // synopsys translate_off
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< // synopsys translate_on
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< `include "uart_defines.v"
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< module uart_debug_if (/*AUTOARG*/
< // Outputs
---
> 
> 
> module uart_debug_if (
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< // Inputs
---
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< input [1:0] 							fcr;  /// bits 7 and 6 of fcr. Other bits are ignored
---
> input [1:0] fcr;
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< always @(/*AUTOSENSE*/fcr or ier or iir or lcr or lsr or mcr or msr
---
> always @(fcr or ier or iir or lcr or lsr or mcr or msr
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< 		                      // 8 + 8 + 4 + 4 + 8
---
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< 		               // 5 + 2 + 5 + 4 + 5 + 3
---
> 
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< 	endcase // case(wb_adr_i)
---
>  endcase
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< endmodule // uart_debug_if
---
> endmodule